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MDT10P57
1. General Description This EPROM-Based 8-bit micro-controller uses a fully static CMOS technology process to achieve higher speed and smaller size with the low power consumption and high noise immunity. On chip memory includes 1K words of ROM, and 128 bytes of static RAM. 2. Features The followings are some of the features on the hardware and software: Fully CMOS static design 8-bit data bus On chip EPROM size: 1K words Internal RAM size: 128 bytes 35 single word instructions 14-bit instructions 8-level stacks Operating voltage: 2.5 V ~ 5.5 V Operating frequency: 0 ~ 20 MHz The most fast execution time is 200 ns under 20 MHz in all single cycle instructions except the branch instruction Addressing modes include direct, indirect and relative addressing modes 3. Applications The application areas range from appliance motor control and high speed automotive to low power remote transmitters/receivers, small instruments, chargers, toy, automobile and PC pe-ripheral ... etc. Power-on Reset Power edge-detector Reset Sleep Mode for power saving 5 types of oscillator can be selected by programming option: INRC--Internal 4MHz RC oscillator RC--Low cost RC oscillator LFXT--Low frequency crystal oscillator XTAL--Standard crystal oscillator HFXT--High frequency crystal oscillator 8-bit real time clock/counter (RTCC) with 8-bit programmable prescaler On-chip RC oscillator based Watchdog Timer (WDT) 4-channel, 8-bit AD Interrupt source: Timer0, INT, Pin change, AD
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P. 1
2007/4
Ver. 1.1
MDT10P57
4. Pin Assignment A1 VDD1 PA52 PA4/AN33 PA34 PB55 PB46 PB37 A2 VDD1 OSC12 OSC23 PA34 PB55 PB46 PB37 14VSS 13PA0/AN0 12PA1/AN1/VREF 11PA2/T0CKI/AN2 10PB0 9PB1 8PB2 VDD1 OSC12 OSC23 MCLRB4 PB55 PB46 PB37 14VSS 13PA0/AN0 12PA1/AN1/VREF 11PA2/T0CKI/AN2 10PB0 9PB1 8PB2 VDD1 PA52 PA4/AN33 MCLRB4 PB55 PB46 PB37 A4 14 VSS 13PA0/AN0 12PA1/AN1/VREF 11PA2/T0CKI/AN2 10PB0 9PB1 8PB2 A3 14 VSS 13PA0/AN0 12PA1/AN1/VREF 11PA2/T0CKI/AN2 10PB0 9PB1 8PB2
5. Pin Function Description Pin Name PA5 PA4/AN3 PA3 PA2/T0CKI/AN2/INT PA1/AN1/VREF PA0/AN0 PB5~PB0 OSC1 OSC2 MCLRB VDD VSS I/O I/O I/O I I/O I/O I/O I/O I O I Function Description Port A, TTL input level / Schmitt Trigger input levels. Port A, TTL input level. Port A, TTL input level / Schmitt Trigger input levels. Input only. Port A, Schmitt Trigger input levels. Port A, TTL input level / Schmitt Trigger input levels. Port A, TTL input level / Schmitt Trigger input levels. Port B, TTL input level. Oscillator Input. Oscillator Output. Master Clear. Power supply Ground
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P.2
2007/4
Ver. 1.1
MDT10P57
6. Memory Map (A) Register Map Address BANK0 00 01 02 03 04 05 06 0A 0B 0C 1E 1F 20~7F BANK1 01 05 06 0C 0E 1F A0~BF TMR CPIO A CPIO B PIEB1 PSTA ADS1 General purpose register Indirect Addressing Register RTCC PCL STATUS MSR Port A Port B PCHLAT INTS PIFB1 ADRES ADCON0 General purpose register Description
(1) IAR (Indirect Address Register): R00 (2) RTCC (Real Time Counter/Counter Register): R01 (3) PC (Program Counter): R02, R0A Write PC --- from PCHLAT Write PC --- from PCHLAT LJUMP, LCALL --- from instruction word RTIW, RET --- from STACK A11 A10~A8 A7~A0
Write PC --- from ALU LJUMP, LCALL --- from instruction word RTIW, RET, RTFI --- from STACK
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P.3
2007/4
Ver. 1.1
MDT10P57
(4) STATUS (Status register): R03 Bit 0 1 2 3 4 5 Symbol C HC Z PF TF RBS0 Function Carry bit Half Carry bit Zero bit Power loss Flag bit WDT Timer overflow Flag bit Register Bank Select bit: 0: 00H~7FH (Bank0) 1: 80H~FFH (Bank1) General purpose bit
7~6
--
(5) MSR (Memory Bank Select Register): R04 Memory Bank Select Register: 0: 00~7F (Bank0) 1: 80~FF (Bank1) b7 b6 b5 b4 b3 b2 b1 b0
Indirect Addressing Mode (6) PORT A: R05 (PA5~PA0, I/O Register) (7) PORT B: R06 (PB5~PB0, I/O Register) (8) PCHLAT: R0A (High byte of PC) Bit 4~0 High byte of PC. 7~5 Unimplemented, reads as '0'. (9) INTS (Interrupt Status Register): R0B Bit 0 1 2 3 4 5 Symbol RAIF INTF TIF RAIE INTS TIS Function PORT A change interrupt flag. Set when PA0, PA1, PA3 inputs change. Set when INT interrupt occurs. INT interrupt flag. Set when TMR0 overflows. 0: disable PA change interrupt. 1: enable PA change interrupt. 0: disable INT interrupt. 1: enable INT interrupt. 0: disable TMR0 interrupt. 1: enable TMR0 interrupt. Function
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P.4
2007/4
Ver. 1.1
MDT10P57
Bit 6 7 Symbol PEIE GIS Function 0: disable all peripheral interrupt. 1: enable all peripheral interrupt. 0: disable global interrupt. 1: enable global interrupt. Function Unimplemented A/D interrupt flag 0: A/D conversion is not complete 1: A/D conversion completed Unimplemented
(10) PIFB1 (Peripheral Interrupt Flag Bit): R0C Bit 0~5 6 7 Symbol -ADIF --
(11) ADRES (A/D result register): R1E (12) ADS0 (A/D Status Register): R1F Bit 0 1 2 4~3 5 7~6 Symbol ADRUN -GO/DONEB CHS1~0 -ASCS1-0 Function 0: A/D converter module is shut off and consumes no operating current 1: A/D converter module is operating Unimplemented 0: A/D conversion in progress 1: A/D conversion not in progress 00: AIC0, 01: AIC1, 10: AIC2, 11: AIC3 Unimplemented 00: fosc/2, 01: fosc/8, 10: fosc/32, 11: f RC (*Note)
*Note: determined by OSC mode, HF: fosc/32, XT: fosc/8, LF: fosc/2, RC: fosc/2 (13) TMR (Time Mode Register): R81 Bit Symbol Prescaler Value 000 001 010 011 100 101 110 111 0: RTCC 1: Watchdog Timer Function RTCC rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 WDT rate 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
2~0
PS2~0
3
PSC
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P.5
2007/4
Ver. 1.1
MDT10P57
Bit 4 5 6 7 Symbol TCE TCS IES PABPH Function 0: Increment on low-to-high transition on RTCC pin 1: Increment on high-to-low transition on RTCC pin 0: Internal instruction cycle clock 1: Transition on RTCC pin 0: Interrupt on falling dege on PA2 1: Interrupt on rising edge on PA2 0: PORTA, PORTB pull-hi are enable 1: PORTA, PORTB pull-hi are disable
(14) CPIO A (Control Port I/O Mode Register): R85 "0", I/O pin in output mode. "1", I/O pin in input mode. (15) CPIO B (Control Port I/O Mode Register): R86 "0", I/O pin in output mode. "1", I/O pin in input mode. (16) PIEB1: R8C Bit 5~0 6 7 (17) PSTA: R8E Bit 1 Symbol PORB Function 0:Power on Reset occurred 1:No Power on Reset occurred Symbol -ADIE -Unimplemented 0: disable A/D interrupt 1: enable A/D interrupt Unimplemented Function
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P.6
2007/4
Ver. 1.1
MDT10P57
(18) ADS1 (A/D Status Register): R9F Bit Symbol Function 0 0 0: PA0~2,PA4= analog input. VREF= VDD. 0 0 1: PA0~2,PA4= analog input. PA1= ref input, VREF= PA1. 0 1 0: PA0~2= analog input. VREF= VDD. 0 1 1: PA0~2= analog input. PA1= ref input, VREF= PA1. PAVM2~0 1 0 0: PA0, 1= analog input. PA2, 4= digital I/O, VREF= VDD. 1 0 1: PA0, 1= analog input. PA2, 4= digital I/O, VREF=PA1. 1 1 0: PA0= analog input. PA1, 2, 4= digital I/O, VREF=VDD. 1 1 1: PA0~2, 4= digital I/O.
2~0
(19) Configurable options for EPROM (Set by writer): Type INRC Oscillator RC Oscillator Type Oscillator HFXT Oscillator XTAL Oscillator LFXT Oscillator Watchdog Timer control Oscillator-start Timer control Power-edge Detect Security state Watchdog timer disable all the time Watchdog timer enable all the time 0ms 80ms PED Disable PED Enable Security Disable Security Enable Option
The default security state of EPROM is weak disable. Once the IC was set to enable or disable, it's forbidden to change. (B) Program Memory Address 000-3FF 000 004 Program memory The starting address of power on, external reset or WDT time-out reset. Interrupt vector Description
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P.7
2007/4
Ver. 1.1
MDT10P57
7. Reset Condition for all Registers Register IAR RTCC PC STATUS MSR PORT A PORT B PCHLAT INTS PIFB1 ADRES ADS0 TMR CPIOA CPIOB PIEB1 PSTA Address 00h 01h 0Ah,02h 03h 04h 05h 06h 0Ah 0Bh 0Ch 1Eh 1Fh 81h 85h 86h 8Ch 8Eh Power-On Reset, Power range detector Reset N/A xxxx xxxx 0000 0000 0000 0001 1xxx xxxx xxxx --xx xxxx --xx xxxx ---0 0000 0000 000x -0-- ---xxxx xxxx 00-0 00-0 1111 1111 --11 1111 --11 1111 -0-- ------- --0/MCLR or WDT Reset N/A uuuu uuuu 0000 0000 0000 000# #uuu uuuu uuuu --uu uuuu --uu uuuu ---0 0000 0000 000u -0-- ---uuuu uuuu 00-0 00-0 1111 1111 --11 1111 --11 1111 -0-- -------- --uWake-up from SLEEP N/A uuuu uuuu PC + 1 000# #uuu uuuu uuuu --uu uuuu --uu uuuu ---u uuuu uuuu uuuu -u-- ---uuuu uuuu uu-u uu-u uuuu uuuu --uu uuuu --uu uuuu -u-- ------- --u---- -uuu
---- -000 ---- -000 ADS1 9Fh Note : uunchanged, xunknown, - unimplemented, read as "0" #value depends on the condition of the following table Condition /MCLR reset (not during SLEEP) /MCLR reset during SLEEP WDT reset (not during SLEEP) WDT reset during SLEEP Power-on reset Power-range reset Status: bit 4 u 1 0 0 1 1 Status: bit 3 u 0 1 0 1 1
PSTA: bit 1 1 1 1 1 0 1
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P.8
2007/4
Ver. 1.1
MDT10P57
8. Instruction Set Mnemonic Operands
Instruction Code
Function No operation Clear Watchdog timer Sleep mode Return from subroutine Store W to register Load register Load immediate to W
Operating None 0WT 0WT, stop OSC StackPC WR Rt IW [R(0~3) R(4~7)]t R + 1t W + Rt R Wt or (R+/W+1t) R 1t R 1t R Wt i WW R Wt i WW R Wt i WW /Rt R(n) R(n-1), CR(7), R(0)C R(n)r(n+1), CR(0), R(7)C 0W 0R 0R(b) 1R(b) Skip if R(b)=0 Skip if R(b)=1
Status
010000 00000000 NOP 010000 00000001 CLRWT 010000 00000010 SLEEP 010000 00000100 RET 010001 1rrrrrrr 011000 trrrrrrr 111010 iiiiiiii 010111 trrrrrrr 011001 trrrrrrr 011010 trrrrrrr 011011 trrrrrrr 011100 trrrrrrr 011101 trrrrrrr 011110 trrrrrrr 010010 trrrrrrr 110100 iiiiiiii 010011 trrrrrrr 110101 iiiiiiii 010100 trrrrrrr 110110 iiiiiiii 011111 trrrrrrr 010110 trrrrrrr 010101 trrrrrrr 010000 1xxxxxxx 010001 0rrrrrrr 0000bb brrrrrrr 0010bb brrrrrrr 0001bb brrrrrrr 0011bb brrrrrrr STWR R LDR R, t LDWI I
TF, PF TF, PF None None Z None None Z None C, HC, Z C, HC, Z Z None Z Z Z Z Z Z Z C C Z Z None None None None
SWAPR R, t Swap halves register INCR R, t Increment register
INCRSZ R, t Increment register, skip if zero R + 1t ADDWR R, t Add W and register SUBWR R, t Subtract W from register DECR R, t Decrement register
DECRSZ R, t Decrement register, skip if zero ANDWR R, t AND W and register ANDWI i IORWR R, t IORWI i XORWI i COMR R, t RRR R, t RLR R, t CLRW CLRR R BCR R, b BSR R, b BTSC R, b BTSS R, b AND W and immediate Inclu. OR W and register Inclu. OR W and immediate Exclu. OR W and immediate Complement register Rotate right register Rotate left register Clear working register Clear register Bit clear Bit set Bit Test, skip if clear Bit Test, skip if set
XORWR R, t Exclu. OR W and register
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P.9
2007/4
Ver. 1.1
MDT10P57
Instruction Code Mnemonic Operands Function Long CALL subroutine Long JUMP to address Add immediate to W Subtract W from immediate Reture from interrupt b T Operating nPC, PC+1Stack nPC W+iW i-WW StackPC,1GIS Status None None C, HC, Z None C, HC, Z None
100nnn nnnnnnnn LCALL n 101nnn nnnnnnnn LJUMP n 110111 iiiiiiii 110001 iiiiiiii 111000 iiiiiiii Note: W WT TMODE CPIO TF PF PC OSC Inclu. Exclu. AND ADDWI i RTIW i SUBWI i
Return, place immediate to W StackPC,iW
010000 00001001 RTFI Working register Watchdog timer TMODE mode register Control I/O port register Timer overflow flag Power loss flag Program Counter HC Oscillator Inclusive `' Exclusive `' Logic AND `'
R C HC Z / x i n
Bit position Target 0 Working register 1 General register General register address Carry flag Half carry Zero flag Complement Don't care Immediate data ( 8 bits ) Immediate address
9. Electrical Characteristics *Note: Temperature=25C 1.Operation Current : (1) HF (C=10p) , WDT - enable 4M 2.5V 3.0V 4.0V 5.0V 5.5V 350uA 530uA 940uA 1.5mA 2.2mA 10M 800uA 1.1mA 1.7mA 2.5mA 3.5mA 20M 1.4mA 1.8mA 2.9mA 4.4mA 6mA Sleep 3uA 8uA 16uA 30uA 50uA
These parameters are for reference only.
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P.10
2007/4
Ver. 1.1
MDT10P57
(2) XT (C=10p) , WDT - enable 1M 2.5V 3.0V 4.0V 5.0V 5.5V 120uA 170uA 310uA 610uA 990uA 4M 300uA 390uA 720uA 1.1mA 1.6mA 10M 800uA 910uA 1.5mA 2.1mA 2.8mA Sleep 3uA 8uA 16uA 30uA 50uA
These parameters are for reference only. (3) LF (C=10p) , WDT - enable 32K(50p) 2.5V 3.0V 4.0V 5.0V 5.5V 20uA 30uA 70uA 140uA 250uA 455K X 80uA 160uA 260uA 360uA 1M 90uA 120uA 220uA 340uA 520uA Sleep 3uA 8uA 16uA 30uA 50uA
These parameters are for reference only. (4) RC , WDT - Enable , @Vdd = 5.0V C R 4.7k 10k 3p 47k 100k 300k 470k 4.7k 10k 20p 47k 100k 300k 470k 4.7k 10k 100p 47k 100k 300k 470k Freq. 6.5M 3.2M 700K 320K 110K 66K 4.2M 2.1M 460K 214K 72K 43K 1.8M 904K 196K 93K 31K 19K Current 1.3mA 790uA 350uA 280uA 250uA 240uA 900uA 600uA 310uA 270uA 250uA 240uA 530uA 370uA 260uA 250uA 240uA 240uA
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P.11
2007/4
Ver. 1.1
MDT10P57
C R 4.7k 10k 300p 47k 100k 300k 470k Freq. 820K 404K 88K 42K 14K 9K Current 350uA 280uA 240uA 230uA 230uA 230uA
These parameters are for reference only. (5) INT_RC , WDT - enable 4MHz 3.0V 4.0V 600uA 900uA Sleep 8uA 16uA
5.0V 1.2mA 30uA These parameters are for reference only. 2. Input Voltage (Vdd = 5V) : Port Vil Vih TTL Schmitt trigger TTL Schmitt trigger Min Vss Vss 2V 3.5V Max 1.0V 1.0V Vdd Vdd
These parameters are for reference only. 3. Output Voltage (Vdd = 5V) : PA,PB Voh Vol Voh Vol 3.5V 0.8V 4.3V 0.6V Condition Ioh =-20mA Iol =+20mA Ioh = -5mA Iol = +5mA
These parameters are for reference only.
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P.12
2007/4
Ver. 1.1
MDT10P57
4. Output Current (Max.) (Vdd = 5V) : Port A: Source current Sink current These parameters are for reference only. Port B: Source current Sink current These parameters are for reference only. 5. The basic WDT time-out cycle time : Time 2.5V 3.0V 4.0V 5.0V 24ms 22ms 19ms 18ms Current 25mA 25mA Current 25mA 25mA
5.5V 17ms These parameters are for reference only. 6.PORTA,PORTB_PULL_RESISTOR @5V,25 Pull_high_resistor PA0,1,2,4,5 PA3 PB0,1,2,3,4,5 50K 340K 50K
UNITS
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P.13
2007/4
Ver. 1.1

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